1. Field of Invention
The present invention relates to wiring substrates, semiconductor devices, semiconductor modules, electronic devices, methods for designing wiring substrates, methods for manufacturing semiconductor devices, and methods for manufacturing semiconductor modules. In particular, the present invention can be applied to chip size packages (CSPs) or ball grid arrays (BGAs).
2. Description of Related Art
In chip size packages and ball grid arrays, ball bumps are disposed with full grids or staggered arrangements. FIG. 12 (a) schematically shows a plan view of the structure of a conventional chip size package, and FIG. 12 (b) shows a cross-sectional view taken along lines J—J of FIG. 12 (a). In FIGS. 12(a) and (b), a semiconductor chip 101 includes a wiring layer 102 that is connected to an active region formed thereon, and pad electrodes 103 are formed on the wiring layer 102. Additionally, a stress buffer layer 104 is formed on the active region formed in the semiconductor chip 101 in a manner to expose the pad electrodes 103, and rearrangement wirings 105 are formed on the pad electrodes 103, which extend over the stress buffer layer 104. Further, a solder resist film 106 is formed on the rearrangement wirings 105, and opening sections 107 are formed in the solder resist film 106, which expose the rearrangement wirings 105 on the stress buffer layer 104. Also, solder balls 108 can be formed over the stress buffer layer 104, and the solder balls 108 are connected to the rearrangement wirings 105 through the opening sections 107 formed in the solder resist film 106.
FIG. 13 (a) schematically shows a plan view of the structure of a conventional ball grid array, and FIG. 13 (b) shows a cross-sectional view taken along lines K—K of FIG. 13 (a). In FIGS. 13(a) and (b), wirings 112a and 112c are formed on both surfaces of an interposer substrate 111, and the wirings 112a and 112c formed on the respective surfaces are mutually connected via through hole wirings 112b that are formed in the interposer substrate 111. Further, a semiconductor chip 113 is mounted on a front surface of the interposer substrate 111, and the semiconductor chip 113 is connected to the wirings 112a via bump electrodes 114, and sealed with molding resin 115. Also, solder balls 116 are disposed in a full grid configuration on a back surface of the interposer substrate 111, and the solder balls 116 are connected to the wirings 112c. 